This design is a 17 GHz direct-downconversion mixer designed by Michael Lynch. It was designed in IBM SiGe technology. The dimensions of the circuit are 1060 um x 910 um, it has a conversion gain of 12 dB, and a double sideband noise figure of 11.5 dB. For more information, see Mike's article from the 2003 RFIC symposium, available on our publications page.

This is a photograph of a 0.13 um CMOS test circuit, designed by Michael Lynch, Josh Nakaska, Bogdan Georgescu, and Chris Holdenried. It measures 1.5 mm x 2.4 mm, and contains low voltage operational amplifiers, interdigitated capacitors, rod matrix capacitors, MIM capacitors, as well as single and multi-layer inductors.

The above photograph is of a 2.5 Gb/s CMOS limiting amplifier that uses modified Cherry-Hooper amplifiers with source-follower feedback. The circuit measures 1440 um x 1440 um, and is designed in 0.18 um CMOS technology. It has 42 dB gain, 2.1 GHz bandwidth, and 14.2 dB noise figure. For more information on this circuit, please refer to the article by Chris Holdenried and Jim Haslett in ESSCIRC 2003, available on our publications page.

The above picture is of a DC-6 GHz SiGe HBT logarithmic amplifier. It will be presented at ISCAS 2004.