Research Areas

From electrical engineering to biology - our members have come from diverse backgrounds. Having such a mixture of talented individuals under one roof allows us to explore many different fields of study related, but not limited to, microelectronics. For example, some of the world's leading research into alternate number systems is produced by our community. We invite you to explore a selection of our publications and learn what our research is all about!

Please note: Placing publications online is a time-consuming task. We plan to eventually host virtually all our publications here, but getting them online will take some time. Your patience is appreciated.

Computer Arithmetic

• A Fast VLSI Systolic Array for Large Modulus Residue Addition
  Journal of VLSI Signal Processing, 1994 (103,144 bytes)
• A New Design Technique for Column Compression Multipliers
  IEEE Transactions on Computers, 1995 (202,659 bytes)
• An Algorithm for Multiplication Modulo 2^n-1
  Proceedings of the 1996 Midwest Symp. on Circ. and Syst., August 18-21, 1996 (36,869 bytes)
• An Efficient Tree Architecture for Modulo 2n+1 Multiplication
  Journal of VLSI Signal Processing, 1996 (98,197 bytes)
• VLSI Digital Signal Processing: Some Arithmetic Issues
  Keynote at SPIE Conference on Advanced Signal Processing, August 1996 (167,566 bytes)

• A Number System with Continuous Valued Digits and Modulo Arithmetic
  IEEE Transactions on Computers, 2001 (171,375 bytes)
• Arithmetic Circuits for Analog Digits
  Proceedings of the International Symposium on Multiple-Valued Logic, 1999 (80,594 bytes)
• Arithmetic with Signed Analog Digits
  Proceedings ARITH14, 1999 (72,776 bytes)

• An algorithm for modular exponentiation
  Information Processing Letters, 1998 (67,535 bytes)
• Complexity and Fast Algorithms for Multi-exponentiation
  IEEE Transactions on Computers, 2000 (147,022 bytes)
• Exponentiation Based on Binary-Fermat Number Representation (ABSTRACT ONLY)
  Internal Report (ATIPS Laboratory), 2001 (12,262 bytes)

• A 2-Digit DBNS Filter Architecture
  Proceedings SiPS Workshop (Lafayette, LA), October 2000 (239,154 bytes)
• A Hybrid DBNS Processor for DSP Computation
  Proceedings International Symposium on Circuits and Systems, 1999 (100,693 bytes)
• A Near Canonic Double-Based Number System (DBNS) with Applications in Digital Signal Processing
  Proceedings SPIE Conference on Advanced Signal Processing, August 1996 (126,745 bytes)
• Non-linear signal processing using index calculus DBNS arithmetic
  Proceedings SPIE Advanced Signal Processing Algorithms, Architectures and Implementations X, 2001 (570,606 bytes)
• On efficient techniques for difficult operations in one and two digit DBNS index calculus
  Proceedings 34th Asilomar Conference on Signals, Systems and Computers, November 2000 (63,213 bytes)
• The use of the multi-dimensional logarithmic number system in DSP applications
  Proceedings 15th IEEE Symposium on Computer Arithmetic, June 2001 (1,140,874 bytes)
• Theory and Applications for a Double-Base Number System
  Proceedings 13th IEEE Symposium on Computer Arithmetic, 1997 (145,343 bytes)
• Theory and Applications of the Double-Base Number System
  IEEE Transactions on Computers, 1999 (228,407 bytes)

• A Flexible Modulus Residue Number System for Complex Digital Signal Processing
  IEE Electronic Letters, 1991 (27,946 bytes)
• An Array Processor for Inner Product Computations Using a Fermat Number ALU
  Proceedings 1995 International Conference on Application Specific Array Processors, 1995 (76,343 bytes)
• Architectures and Implementations for the Polynomial Ring Engine over Small Residue Rings
  Ph.D. Thesis, 1997 (2,142,565 bytes)
• Efficient Fault-Tolerant Arithmetic using a Symmetrical Modulus Replication RNS
  Proceedings 2001 SiPS Workshop (Belgium), September 2001 (53,307 bytes)
• Exploiting Redundancy in Modulus Replication Inner Product Processors
  Ph.D. Thesis, 1999 (2,894,882 bytes)
• Fault-Tolerant Computation of Large Inner Products
  IEE Electronics Letters, April 2001 (54,138 bytes)
• General purpose FIR filter arrays using optimized redundancy over direct product polynomial rings
  1998 Asilomar Conference on Systems, Signals and Computation, November 1998 (94,235 bytes)
• High Throughput VLSI DSP Using Replicated Finite Rings
  Journal of VLSI Signal Processing, 1996 (185,315 bytes)
• Large Dynamic Range Computations over Small Finite Rings
  IEEE Transactions on Computers, 1994 (205,421 bytes)
• On Moduli Replication for Residue Arithmetic Computations of Complex Inner Products
  IEEE Transactions on Computers (Special Issue on Computer Arithmetic), August 1990 (193,776 bytes)
• Using Redundant Finite Rings for Fault Tolerant Signal Processors
  Proceedings SPIE Advanced Signal Processing: Algorithms, Architectures and Implementations V, 1994 (97,118 bytes)
• VLSI Implementations of Number Theoretic Concepts with Applications in Signal Processing
  Handbook of Statistics, N.K. Bose & C.R. Rao (editors), Elsevier Science Publishers, 1993 (245,103 bytes)

• A Fast and Robust RNS Algorithm for Evaluating Signs of Determinants
  Computers and Mathematics with Applications, 1998 (133,859 bytes)
• A Residue Number System Implementation of Real Orthogonal Transforms
  IEEE Transactions on Signal Processing, 1998 (146,965 bytes)
• An Efficient 3-Modulus Residue to Binary Converter
  Proceedings of the 1996 Midwest Symposium on Circuits and Systems (Ames, Iowa), August 18-21, 1996 (42,192 bytes)
• An Improved Residue-to-Binary Converter
  IEEE Transactions on Circuits and Systems I, 2000 (64,195 bytes)
• Comments on An Arithmetic Free Parallel Mixed-Radix Conversion Algorithm
  IEEE Transactions on Circuits and Systems II, 1999 (29,786 bytes)
• Eisenstein Residue Number System with Applications to DSP
  Proceedings 1997 Midwest Symposium on Circuits and Systems, 1997 (43,653 bytes)
• FPGA Implementation Of RNS Structures
  M.A.Sc. Thesis, 1994 (544,945 bytes)
• FPGA Implementation of Residue Number System Structures
  1995 IEEE Symposium on Circuits and Systems, 1995 (27,667 bytes)
• Fault Detection for a Systolic Array Cell
  IEE Electronics Letters, February 1987 (39,235 bytes)
• Fault-tolerant Techniques for Finite Ring Arithmetic Processors
  Internal ATIPS Report, 1987 (160,759 bytes)
• High Speed Signal Processing using Systolic Arrays Over Finite Rings
  IEEE Transactions on Selected Areas in Communications, April 1988 (175,202 bytes)
• Homogeneous VLSI Structures for Finite Ring Computations
  Proceedings of the 7th Kobe International Symposium on Electronics and Information Sciences, November 1988 (52,274 bytes)
• Homogeneous VLSI Structures for High Speed DSP using Number Theoretic Techniques
  Proceedings of the 1989 SPIE Conference (San Diego), August 6-11, 1989 (92,080 bytes)

Analog Design

• A 0.18um CMOS Bluetooth Frequency Synthesizer for Integration with a Bluetooth SOC Reference Platform
  Proceedings of The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003/07/01 (938,306 bytes)
• A 1.5V 12mW Silicon Receiver Front-end with a 65dB Image Rejection
  CMC Texpo 2003, 2003/06/01 (596,208 bytes)
• A 10 GB/S LOGARITHMIC AMPLIFIER FOR OPTICAL SINGLE SIDEBAND
  TRLabs TechForum 2002, 2002/10/01 (1,855,034 bytes)
• A 17-GHz Direct Down-Conversion Mixer in a 47-GHz SiGe Process
  2003 Radio Frequency Integrated Circuit Symposium, 2003/06/01 (377,287 bytes)
• A DC-4 GHz Logarithmic Amplifier with Fiber-Optic Applications
  Proceedings of Wireless 2001, 2001/07/09 (403,628 bytes)
• A DC-6 GHz, 50 dB Dynamic Range, SiGe HBT True Logarithmic Amplifier
  2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004), 2004/05/24 (287,585 bytes)
• A DC-6 GHz, 50 dB Dynamic Range, SiGe HBT True Logarithmic Amplifier (Presentation)
  2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004), 2004/05/24 (602,127 bytes)
• A DC–4-GHz True Logarithmic Amplifier: Theory and Implementation
  IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002/10/01 (450,837 bytes)
• A Fully Integrated Active Inductor with Independent Voltage Tunable Inductance and Series-Loss Resistance
  IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2001/04/01 (227,230 bytes)
• A High Speed Complex Adaptive Filter For an Asymmetric Wireless LAN Using a New Quantized Polynomial Representation
  ISCAS 2003, 2003/03/03 (438,898 bytes)
• A LIMITING AMPLIFIER USING MODIFIED CHERRY-HOOPER STAGES IN 0.18um CMOS
  CMC Texpo 2003, 2003/06/01 (1,536,729 bytes)
• A Novel Gigabit Radio Transceiver for System-on-a-Chip Wireless LAN
  2002 International Workshop on System-on-Chip, 2002/07/01 (172,515 bytes)
• A Novel Gigabit Radio Transceiver for System-on-a-Chip Wireless LAN (Poster)
  2002 International Workshop on System-on-Chip, 2002/07/01 (851,544 bytes)
• A Square-Rooting Voltage-to-Frequency Converter
  IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 1997/10/01 (461,889 bytes)
• A modulus replication complex-adaptive-filter IP core
  Canadian Journal of Electrical and Computer Engineering, 2002/10/01 (222,977 bytes)
• An Analytic Model for Estimating the Length of the Velocity Saturated Region in GaAs MESFET’s
  IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000/06/01 (219,673 bytes)
• Analysis and Design of HBT Cherry–Hooper Amplifiers With Emitter-Follower Feedback for Optical Communications
  Journal of Solid State Circuits, 2004/11/01 (1,085,111 bytes)
• Asymmetric Orthogonal Frequency Division Multiplexing
  Proceedings of Wireless 2000, 2000/06/01 (79,821 bytes)
• BiCMOS Adjustable Linear Current Mirror
  IEEE Journal of Solid-State Circuits, 1997/01/01 (712,528 bytes)
• Broadband DSP based feedforward amplifier linearizer
  ELECTRONIC LETTERS, 2002/11/01 (375,127 bytes)
• Characterization of EM Downhole-to-Surface Communication Links
  IEEE TRANSACTIONS ON GEOSCIENCE AND REMOTE SENSING, 2000/11/01 (298,300 bytes)
• DC - 4 GHZ LOGARITHMIC AMPLIFIER
  TRLabs TechForum 2001, 2001/10/01 (273,631 bytes)
• GigaRFIC Phase I: 17 GHz LNA & Mixer
  CMC Texpo 2002, 2002/06/18 (1,195,355 bytes)
• Integrated GHz Voltage-Controlled Oscillators in a 47GHz SiGe Process
  Proceedings of Wireless 2003 (Presentation), 2003/07/01 (3,209,696 bytes)
• Integrated GHz Voltage-Controlled Oscillators in a 47GHz SiGe Process
  Proceedings of Wireless 2003, 2003/07/01 (751,140 bytes)
• LOGARITHMIC AMPLIFIER
  US Patent Application, 2003/02/13 (1,209,811 bytes)
• Modified CMOS Cherry-Hooper Amplifiers with Source Follower Feedback in 0.35um Technology
  2003 European Solid State Circuits Conference, 2003/09/01 (463,982 bytes)
• Monolithic Transformer Compensated Circuit
  US Patent Application, 2003/07/01 (773,128 bytes)
• Monolithic Tunable Active Inductor with Independent Q Control
  IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2000/06/01 (253,211 bytes)
• Neural-Network Approaches to Electromagnetic-Based Modeling of Passive Components and Their Applications to High-Frequency and High-Speed Nonlinear Circuit Optimization
  IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2004/01/01 (807,892 bytes)
• Noise Analysis of a Continuous-Time Auto-Zeroed Amplifier
  IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING, 1996/12/01 (1,232,279 bytes)
• Pushing the Speed Limits of Technology for RF IC Design
  MRDCAN 2003 Presentation, 2003 (2,222,276 bytes)
• RFIC Research
  TRLabs TechForum 2003, 2003/07/01 (1,879,740 bytes)
• Simulation of Temperature Cycling Effects on Electromigration Behavior Under Pulsed Current Stress
  IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998/02/01 (216,182 bytes)
• Subthreshold Analysis of an MOS Analog Switch
  IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997/01/01 (405,482 bytes)
• The Design of a 17.35 GHz LNA and Mixer
  Proceedings of Wireless 2002, 2002/07/01 (682,051 bytes)
• The Design of a 17.35 GHz LNA and Mixer (Presentation)
  Proceedings of Wireless 2002, 2002/07/01 (927,376 bytes)
• Tunable Coupled Inductor Q-Enhancement for Parallel Resonant LC Tanks
  IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, 2003/10/01 (769,294 bytes)
• Two Baseband Logarithmic Amplifier Designs Using Parallel Feedback Amplifier Cells
  Proceedings of Wireless 2002, 2002/07/09 (274,238 bytes)
• Two Baseband Logarithmic Amplifiers Using Parallel Feedback Amplifier Cells
  CMC Texpo 2002, 2002/10/01 (812,724 bytes)